In U.S. Pat. No. 4,325,120 of Stephen R. Colley, et al. entitled "Data Processing System," granted Apr. 13, 1982, there is disclosed an object-oriented data processor architecture which takes full advantage of recent advances in the state-of-the-art of very large-scale, integrated-circuit technology. That patent application describes a general-purpose data processor (GDP) which is able to perform generalized computation over a wide spectrum of data types supported by the architecture. There is a need to provide an interface between a peripheral subsystem environment (for example, a processor such as an Intel 8085 or 8086, local memory, and a local bus, such as an Intel Multibus or a processor bus) and the GDP system's protected main memory environment. The architecture of such an interface is described in U.S. Pat. No. 4,315,310 of John Bayliss, et al. entitled "Input/Output Data Processing System," granted Feb. 9, 1982. The input/output data processing system described therein provides an interface by which an attached processor is connected to the main data processing system. It includes means for addressing the main memory as well as means for providing function compatibility with the GDP system's object-oriented architecture. The interface is able to recognize addresses generated by the attached processor, and map these addresses onto the address space of GDP main memory. The interface also allows the attached processor to communicate with processes and processors within the data processing system.
Because of its role as an interface between the main memory space and the peripheral subsystem, the data transfer rate between the two systems should be optimized. Not only should the data rate by optimized, there must be provided means to support the execution of microinstructions from the peripheral subsystem in order to implement a function-request facility which provides a functional capability over certain objects within the main processor's address space.
Since address translation necessarily takes a certain amount of time, it would be inefficient to go through an address translation for each byte or word of data to be transferred from the peripheral subsystem to the main memory.
It is therefore a primary object of the present invention to provide an improved microprocessor which establishes an interface to enable a peripheral subsystem to access portions of the main memory of a data processing system in a controlled and protected manner, by means of address-mapping facilities, whereby data blocks may be transferred without going through an address translation for each one of the bytes or words comprising a data block.